The present invention relates to programmable logic arrays and, more particularly, to a complementary metal-oxide-semiconductor (CMOS) form of programmable logic array (PLA) which is fully static and consumes substantially zero power in a stationary state.
It is well known that one important integrated circuit building block is the programmable logic array, in which a relatively large plurality of input binary logic terms can be combined, according to particular logic equations worked out by the system designer, to provide output logic terms unique to a particular use. Typically, a PLA utilizes a set of AND or NAND gates to provide intermediate logic terms, sometimes referred to as minterms. A second group of gates may be utilized to provide the logic OR or NOR of selected minterms, to derive the output terms. In some PLAs, the various interconnections can be made in the field (so-called field programmable PLAs), rather than by the interconnection means, e.g. metalization masking patterns, which are introduced during the integrated circuit fabrication. Similarly, the interconnective mask patterns can be so arranged that some of the output terms are fed back to become certain of the input signals, so that the PLA can be utilized to realize a finite-state machine.
A PLA can have a relatively simple form if n-channel technology is utilized for the MOSFET devices of the PLA; this relatively simple form suffers from several undesirable characteristics, including the consumption of power even when the PLA is in a "stationary" state, i.e. the input terms are not in a state of change. It is also well known that integrated circuitry provided with complementary MOSFET devices (CMOS integrated circuitry) will provide no-power stationary states, but will not have the relatively simple form of NMOS integrated circuits, as a large number of series-connected n-channel devices, equal to the number of inputs necessary to form the minterms in the AND plane, are required. Thus, fully-featured CMOS PLAs are either very slow, if standard NAND gates are formed with long serial chains of n-channel transistors, or lose some of the desired CMOS features, if faster structures are employed. A CMOS PLA can be formed with "domino" logic structures, which, while small and fast, are dynamic and have a minimum operating frequency. Likewise, circuits with pull-up devices can be made small and fast, but require a current flow to exist at all times. Hitherto, a completely satisfactory circuit solution, resulting in full CMOS logic features, in a programmable logic array, has not been realizable.